Analysis of a Peak Detection Algorithm Using System-on-chip Architecture

Peak detection is widely used in many signal-processing applications, since it allows automatic signal processing and produces faster result for users. In this work, an analysis of a peak detection algorithm implemented into a fieldprogrammable gate array (FPGA) is discussed. A system-on-chip (SoC) hardware architecture was designed using the Altera platform to analyse the system data flow. A set of 1000 random data was executed by the peak detection algorithm in the SoC architecture. The output result obtained from the architecture were verified with the result obtained from a Matlab simulation. Based on the power consumption report, the reported power disipation of the system architecture is 202.79 mW.